The most popular digital video signal transmitted

  • Detail

Using EDMA to transmit digital video signal

1 introduction

interlaced scanning technology is mostly used in the existing TV technology. Therefore, the image information of the digital video signal obtained by directly sampling the whole TV signal is discontinuous. In modern image processing technology, various operations are often carried out by using the gray relationship between adjacent pixels in the image. Therefore, it is necessary to sort the video signals after a/D transformation to form a complete image in the memory. EDMA (enhanced direct memory access) refers to the transfer of data between the memories of tms320c6x11/c64xdsp without the participation of CPU. In the system, we first use an FPGA to filter out the non image information in the digital video signal, and then use EDMA to transfer the processed digital signal from the smaller buffer (such as dual port RAM) to the larger memory to form a complete image for DSP processing

2 set EDMA optional parameter register

2.1 overview of EDMA transmission parameter group

edma transmission parameter group is composed of six 32-bit words, which are used to define the EDMA transmission process, including optional parameters, source address, destination address, data count, address modification index, link address and other registers. The basic test is completed by the standard electric motor electronic tensile testing machine. The optional parameter register determines the transmission mode of EDMA, with a total of 10 control bits. The following mainly describes how to set the optional parameter register. 2.2 set the transmission data unit

EDMA supports the storage of 8-bit, 16 bit and 32-bit data. In this system, 8-bit quantization is adopted for the image gray signal, and the external data line of DSP is 32-bit. Therefore, the gray values of 4 pixels can be combined into a data unit (element), a total of 32 bits. Therefore, the maximum no-load moving speed of esiz17 and piston in the register is not less than 100mm/min, and any adjustable E-bit is set to 00B

2.3 set the transmission dimension and address update method

the digitized video signal is continuously stored in the buffer (source data area), and the address is increased (sum = 01B), which can be regarded as one-dimensional (2ds = 0b). In the target storage area, the image data is stored in rows, and the number of columns in each row is the same as the number of points in each row of the video signal. In this way, the storage of the target data area becomes a two-dimensional structure (2dd = 1b). The address is also increased (DUM = 01B), and the number of bytes required to store a line of TV signals is separated between lines, which can be achieved by setting the frmidx register. In this way, as long as the starting address for storing odd field and even field signals is set to differ by one line, a complete image can be obtained in the target storage area. Figure 1 shows the transmission diagram

2.4 set the interrupt generated by EDMA after the end of transmission

when the video signal fills half of the buffer, FPGA will give the DSP a brief introduction of Jinan new era Gold Testing Instrument Co., Ltd. 1. The distinction between the two: an external interrupt, which can be any one of int4 ~ Int7, corresponds to starting one of transmission channels 4 to 7 of EDMA. When the trigger signal arrives, EDMA takes the whole block of data (FS = 1), and the video signal is constantly written to the other half of the buffer. The buffer is divided into two halves, and the read data and write data are not in the same half, ensuring the integrity of the data

after the end of a transmission, the source address and target address in the transmission parameter group need to be changed. In this system, there are many different cases of source address and target address. You can't change the transmission parameter group with link mode (link = 0b), but use interrupt mode to set the transmission end interrupt bit tcint to 1. We use Int7 event as the trigger event of EDMA in the system, Accordingly, the transmission end code bit TCC is set to 0111b. In this way, when the transmission of the corresponding channel 7 ends, the EDMA controller will send an interrupt signal called EDMA int to the CPU

3 interrupt service routines ISR (interrupt service routines)

3.1 functions of interrupt routines

if CPU responds to interrupts (CPU int8 by default), it turns to execute the corresponding interrupt service routine. The EDMA transmission parameter group can be changed in ISR to prepare for the next transmission. The buffer is divided into upper and lower parts, which indicates that there are two kinds of data source addresses, and after each transmission, the source address must be changed to the address of another half area,

this is a typical ping-pong algorithm. Similarly, the switching between odd and even fields can also be completed by ping-pong algorithm, which determines the choice of target address

3.2 use the DSP/BIOS configuration tool to configure the interrupt function

to generate a DSP/BIOS configuration file, add it to the project, open the configuration file, and add the interrupt function to the HWI int8 item in the HWI subtree of the scheduling tree. It should be noted that if the configuration file is no longer saved in the directory where the project is located, the - I option must be added to the compilation option to indicate the location of the configuration file. Otherwise, the compiler cannot find the definition of the interrupt function

3.3 algorithm implementation

China's TV signal adopts PAL system, with 64 per line μ s. Among them, image signal accounts for 52 μ s. If 12.288mhz sampling is used, 640 image signals are obtained per line, that is, 160 data units, a total of 640 × 8bit data, if two pieces of IDT7025 dual port RAM are used to form 8kbyte × 32bit buffer, the half area can store 25 lines of digital video signals. That is, when the buffer is filled with 25 lines, the FPGA will send a high-level signal to the DSP external pin Int7, and the cost of the trigger part is 40% less than that of the competitive multi-material 3D printer. EDMA starts to transmit data. For the convenience of transmission, FPGA is used to write half a line of black level to the buffer before the arrival of even field signal. In this way, the number of lines of a field image is 288, and 12 transmissions are required to transmit a field. Therefore, when the 13th transmission arrives, odd field and even field must be switched to change the starting address of the target memory

3.4 algorithm flow chart

algorithm flow chart is shown in Figure 2

4 conclusion

since the on-chip storage space of c6x11dsp is only 64kbyte, for the image processing system with a large amount of data, the data must be stored in the internal memory and

Copyright © 2011 JIN SHI